In an effort to port RIOT to SmartFusion2 (goto BACKGROUND at the bottom for interest), we’ve hit a small stumbling block. The dedicated hardware timer is extremely basic and does not have any CCP (capture/compare) channels. It’s is a simple down counter with an overflow interrupt.
This seems to be a bit of a show stopper in regard to periph/timer.h and xtimer: int timer_set_absolute(tim_t dev, int channel, unsigned int value);
We’ve tried to keep the FPGA realm out of the equation as an initial strategy, since it could contain anything and we need to devise a structure that will fit with RIOT for the FPGA contents. That said we could implement a timer core with the necessary functionality and use it for periph/timer.h and xtimer …
Would that be the best or are we overlooking another option?
BACKGROUND: SF2 is a device that interfaces low power FPGA fabric with a hard-wired CortexM3. It has a few basic (optional) peripherals, but the FPGA practically opens up endless options. Currently we have two basic examples (default, hello-word) running on the SF2-STARTER-KIT board, with a M2S010 SF2 device. We reckon this is an exiting development - it seems that FPGAs are currently not really featuring in this space - but offer unique field upgrading of hardware subsystems e.g. security blocks or edge data processing algorithms.
Kind Regards, Gideon