Hi guys,
so far it’s only an experiment, but I’ve started porting RIOT OS to the icoBoard Lattice FPGA / icoSoC / picorv32 RISC-V softcore CPU platform.
The Lattice chip used on the icoBoard is probably the only FPGA device supported by open source tools. And it will be the first FPGA device supported by RIOT OS (AFAIK)
RIOT OS already supports the HiFive E310 RISC-V MCU, but that is a very different piece of hardware with RISC-V Privileged Architecture support. Still I’ve been able to reuse some code chunks.
So far It’s only an experiment (and I’m a newbie at this!), but all the important features already work, including shell over UART. It is really fascinating to be able to use a tiny FPGA board this way.
If you are interested, you can find the (alpha, experimental!) code at:
https://github.com/tstyblo/RIOT-icoboard
It would make no sense trying to merge it into the mainline now, as the code needs a lot of testing, comments and improvements. But I’d like to use this opportunity to invite anyone interested in FPGA devices or in the RISC-V platform to check it out.
Regards,
Hi Tomas,
Hi guys,
so far it's only an experiment, but I've started porting RIOT OS to
the icoBoard Lattice FPGA / icoSoC / picorv32 RISC-V softcore CPU
platform.
The Lattice chip used on the icoBoard is probably the only FPGA device
supported by open source tools. And it will be the first FPGA device
supported by RIOT OS (AFAIK)
I think you're right with this. I haven't heard of anybody running RIOT
on an FPGA softcore before. Doesn't mean that they don't exist of course 
RIOT OS already supports the HiFive E310 RISC-V MCU, but that is a
very different piece of hardware with RISC-V Privileged Architecture
support. Still I've been able to reuse some code chunks.
I happen to be working on refactoring the fe310 code to split out the
common RISC-V code bits. Mainly to support the gd32vf103 devices from
Gigadevice, but any RISC-V MCU should benefit from this. It should at
least simplify your porting work in the future.
So far It's only an experiment (and I'm a newbie at this!), but all
the important features already work, including shell over UART. It is
really fascinating to be able to use a tiny FPGA board this way.
(Personally) I think this makes for a great addition to RIOT. Support
for a softcore really opens a lot of options for designers.
If you are interested, you can find the (alpha, experimental!) code at:
GitHub - tstyblo/RIOT-icoboard: RIOT OS for icoBoard FPGA with picorv32 RISC-V core
It would make no sense trying to merge it into the mainline now, as
the code needs a lot of testing, comments and improvements. But I'd
like to use this opportunity to invite anyone interested in FPGA
devices or in the RISC-V platform to check it out.
Looks awesome, thanks for sharing. Is there also a repository with the
verilog for the FPGA configuration? Any estimation how many LUT's and
other resources it requires from the FPGA?
Best regards,
Koen Zandberg
Hi Koen,
thank you for checking it out.
All the Verilog code for the CPU and the SoC peripherals is at:
https://github.com/cliffordwolf/picorv32
https://github.com/cliffordwolf/icotools/tree/master/icosoc
The schematics for the board are available. The Lattice FPGA chip and the auxiliary ICs (FTDI,SRAM,FLASH) are of course proprietary.
On the software side the only problem is that it is difficult to configure the PLL clock generator without using values provided by the proprietary Lattice iceCube software. I have not found any open source tool for that, and the official documentation does not say much about it unfortunately.
I’ve already made some additions to the SoC code (RX interrupts for the console and serial UARTS and other things) so it is necessary to patch the icoSoC code with the patch linked in the RIOT-icoboard documentation. That also provides a common configuration for testing.
Integrating it all in a user-friendly way is actually the most difficult part of the project.
The basic picorv32 + icoSoC configuration that I’m using (no MUL/DIV, 20 MHz) needs about 5K LUTS, so there are plenty of free cells for custom peripherals created in Verilog.
IOs 82 / 206
GBs 1 / 8
GB_IOs 0 / 8
LCs 4565 / 7680
DFF 1298
CARRY 521
CARRY, DFF 140
DFF PASS 582
CARRY PASS 106
BRAMs 18 / 32
WARMBOOTs 0 / 1
PLLs 1 / 2
Regards,