Dual-core usage of STM32WL55 line

leo · 14 September 2026 13:09

Hello,

I’m using a nucleo board using an STM32WL55JC1 which is based on a dual-core architecture.

I want my application to be as low-power as possible, at the moment i’m reaching 1.6 mA (by switching the main core to stop mode). I was wondering how the multi-core architecture are handled in riot-os.

Can i use the second CPU?

Is this second CPU clocked by default or do i need to “turn it off” by a mean or another to decrease power consumption?

Have a nice day

crasbe · 15 September 2026 09:12

Hello,

currently there is no support for a second CPU or core in RIOT at all for any platform.

I’m not sure if the second core is explicitly disabled, but it certainly is not enabled by any code. That would be something to look up in the STM32WL55 reference manual I guess and compare it with the platform specific code in RIOT.

In theory you can use the second cores, but there are no provisions in RIOT to help you with that. That means you’ll have to compile and load a program separately and implement a means of communication between the cores.

The STM32WL55 datasheet has some information about power usage of the core(s) and different components that will give you an idea whether or not the power consumption you’re currently seeing is within what’s to be expected or not. The power consumption mainly depends on the clock frequency, which AFAIR is set to the maximum in RIOT. You can decrease the clock frequency to save some power.

There are some pre-configured default frequencies, but other than that you’ll have to set the PLL values manually, which can be a bit tricky. The easiest approach is to define the clock tree with STM32CubeMX and then read off the values from there and populate the respective configuration defines. For reference you can take a look at these files:

github.com/RIOT-OS/RIOT

cpu/stm32/stmclk/stmclk_l4wx.c

master

/*
 * SPDX-FileCopyrightText: 2017 Freie Universität Berlin
 * SPDX-FileCopyrightText: 2017 OTA keys S.A.
 * SPDX-FileCopyrightText: 2017 HAW-Hamburg
 * SPDX-License-Identifier: LGPL-2.1-only
 */

/**
 * @ingroup     cpu_stm32
 * @{
 *
 * @file
 * @brief       Implementation of STM32 clock configuration for L4 and WB families
 *
 * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
 * @author      Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
 * @author      Vincent Dupont <vincent@otakeys.com>
 * @author      Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
 * @author      Francisco Molina <francois-xavier.molina@inria.fr>
 * @}

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github.com/RIOT-OS/RIOT

boards/nucleo-wl55jc/include/periph_conf.h

master

/*
 * SPDX-FileCopyrightText: 2021 Freie Universität Berlin
 * SPDX-License-Identifier: LGPL-2.1-only
 */

#pragma once

/**
 * @ingroup     boards_nucleo-wl55jc
 * @{
 *
 * @file
 * @brief       Peripheral MCU configuration for the nucleo-wl55jc board
 *
 * @author      Akshai M <akshai.m@fu-berlin.de>
 * @author      Hauke Petersen <devel@haukepetersen.de>
 *
 */

/* Add specific clock configuration (HSE, LSE) for this board here */

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github.com/RIOT-OS/RIOT

cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h

master

/*
 * SPDX-FileCopyrightText: 2017 Freie Universität Berlin
 * SPDX-FileCopyrightText: 2019 Inria
 * SPDX-License-Identifier: LGPL-2.1-only
 */

#pragma once

/**
 * @ingroup     cpu_stm32
 * @{
 *
 * @file
 * @brief       Default STM32L4 clock configuration
 *
 * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
 * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
 */

#include "cfg_clock_common_lx_u5_wx.h"

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Best regards,

Chris

leo · 17 September 2026 09:26

OK thanks,

I will read the datasheet, and see if i can manually configure register (is there any function to read/write register in stm32 or do i use just a pointer to the register location).

Thank you very much for your answer : )